Grupos de investigación

  1. Portada
  2. Publicaciones

Publicaciones

 

  • M. Rezaei, G. Hubert, P. Martín-Holgado, Y. Morilla, J. C. Fabero, H. Mecha, F. J. Franco, H. Puchner and J. A. Clemente, “Impact of Dynamic Voltage Scaling on SEU Sensitivity of COTS Bulk SRAMs and A-LPSRAMs against Proton Radiation”, IEEE Transactions on Nuclear Science (TNS), vol. 69, no. 2, Feb. 2022. (JCR: Q2 as of 2020)
  • J.A. Bravo-Montes, A. Martin-Toledano, A. Sánchez-Macián, O.Ruano, F. Garcia-Herrero, "Design and implementation of efficient QCA full-adders using fault-tolerant majority gates", The Journal of Supercomputing, Springer, 2022 (in press). https://doi.org/10.1007/s11227-021-04247-9. (JCR: Q2).
  • J. A. Clemente, M. Rezaei and F. J. Franco, "Reliability of Error Correction Codes Against Multiple Events by Accumulation," in IEEE Transactions on Nuclear Science, vol. 69, no. 2, pp. 169-180, Feb. 2022, doi: 10.1109/TNS.2022.3143652  (JCR: Q2 as of 2020).
  •  L. Rodriguez-Soriano, O. Ruano, F. Garcia-Herrero, J.A. Maestro, "A New Radiation-Hardened Architecture for Holographic Memory Address Calculation", Alexandria Engineering Journal, Elsevier (ISSN: 1110-0168), Vol. 61, No 8, August 2022, pp. 6181-6190. DOI: 10.1016/j.aej.2021.11.049. [IF(2020)= 3.732; Q1(2019)= 21/90]
  • Y. M. Kuo, F. Garcia-Herrero, O. Ruano, J.A. Maestro, "Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors", Computers and Electrical Engineering, Elsevier (ISSN: 0045-7906), Vol. 99, April 2022, pp. 1-13. DOI: 10.1016/j.compeleceng.2022.107759. [IF(2020)= 3.818; Q2(2020)= 14/53]
  • K. W. Gear, A. Sánchez-Macián, J.A. Maestro, "An Analysis of FPGA Configuration Memory SEU Accumulation and a Preventative Scrubbing Technique", Microprocessors and Microsystems, Elsevier (ISSN: 0141-9331), Vol. 90, April 2022, pp. 1-13. DOI: 10.1016/j.micpro.2022.104467. [IF(2020)= 1.525; Q3(2020)= 37/53]
  • A. Sanchez-Macian, A. Martin-Toledano, J. A. Bravo-Montes, F. Garcia-Herrero and J. A. Maestro, "Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale," in IEEE Transactions on Emerging Topics in Computing, doi: 10.1109/TETC.2021.3136204. (JCR: Q1).
  • J. A. Clemente, G. Hubert, M. Rezaei, F. J. Franco and H. Mecha, "Impact of the Bitcell Topology on the Multiple-Cell Upsets Observed in VLSI Nanoscale SRAMs," in IEEE Transactions on Nuclear Science, vol. 68, no. 9, pp. 2383-2391, Sept. 2021, doi: 10.1109/TNS.2021.3099202  (JCR: Q2 as of 2020).
  • The CTA Collaboration, “Sensitivity of the Cherenkov Telescope Array to a dark matter signal from the Galactic centre,” in Journal of Cosmology and Astroparticle Physics, Vol. 2021, no. 1, Jan. 2021, doi: 10.1088/1475-7516/2021/01/057  (JCR: Q1 as of 2020)
  • The CTA Collaboration, “Sensitivity of the Cherenkov Telescope Array for probing cosmology and fundamental physics with gamma-ray propagation,” in Journal of Cosmology and Astroparticle Physics, Vol. 2021, no. 2, Feb. 2021, doi: 10.1088/1475-7516/2021/02/048  (JCR: Q1 as of 2020)
  • J. Valls, F. Garcia-Herrero, N. Raveendran, B. Vasić, "Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes", IEEE Access (ISSN: 2169-3536), Vol. 9, October 2021, pp. 138734-138743, doi: 10.1109/ACCESS.2021.3118544. (JCR: Q2).
  • S. Bernabé, C. González, A. Fernández and U. Bhangale, "Portability and Acceleration of Deep Learning Inferences to Detect Rapid Earthquake Damage From VHR Remote Sensing Images Using Intel OpenVINO Toolkit", IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing, Vol. 14, pp. 6906-6915, 2021. (JCR: Q2)
  • L. A. Aranda, O. Ruano, F. Garcia-Herrero, J.A. Maestro, "Reliability Analysis of ASIC Designs with Xilinx SRAM-Based FPGAs", IEEE Access (ISSN: 2169-3536), Vol. 9, October 2021, pp. 140676-140685. DOI: 10.1109/ACCESS.2021.3119633. [IF(2020)= 3.367; Q2(2020)= 94/273]
  • A. Alcolea, J. Olivito, J. Resano and H. Mecha, “Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Vol. 28, no. 9, pp. 1993-2003, 2020, (JCR: Q3)
  • F. Garcia-Herrero, A. Sánchez-Macián, J.A. Maestro, "Combined Symbol Error Correction and Spare Through-Silicon Vias for 3D Memories", IEEE Transactions on Emerging Topics in Computing (ISSN:), Vol. 9, No 4, October - December 2021, pp. 2139-2145. DOI: 10.1109/TETC.2020.2965193. [IF(2020)= 7.691; Q1(2020)= 11/161]
  • F. García-Herrero, G. McGuire, M.F. Flanagan, A. Sánchez-Macián, J.A. Maestro, "Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and its Derived Architectures", IEEE Transactions on Circuits and Systems II (ISSN: 1549-7747), Vol. 68, No 4, April 2021, pp. 1438-1442. DOI: 10.1109/TCSII.2020.3038462. [IF(2020)= 2.571; Q2(2020)= 81/319]
  • K. W. Gear, A. Sánchez-Macián, J.A. Maestro, "Reduced Length Redundancy Adaptive Protection for the Cascaded Integrator-Comb Interpolation Filter on FPGA", Microelectronics Reliability, Elsevier (ISSN: 0026-2714), Vol. 118, March 2020, pp. 1-6. DOI: 10.1016/j.microrel.2021.114043. [IF(2020)= 1.589; Q3(2020)= 196/273]
  • O. Ruano, F. García-Herrero, L.A. Aranda, A. Sánchez-Macián, L. Rodríguez, J.A. Maestro, "Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial", Sensors, MDPI (ISSN 1424-8220), Vol. 21, No 4, February 2021, pp. 1-23. DOI: 10.3390/s21041392. [IF(2020)= 3.576; Q1(2020)= 14/64]
  • F. García-Herrero, A. Sánchez-Macián, J.A. Maestro, "Low delay non-binary error correction codes based on Orthogonal Latin Squares", Integration, Elsevier (ISSN: 0167-9260), Vol. 76, January 2021, pp. 55-60. DOI: 10.1016/j.vlsi.2020.09.004. [IF(2020)= 1.211; Q4(2020)= 46/53]
  • L. A. Aranda, F. García-Herrero, L. Esteban, A. Sánchez-Macián, J.A. Maestro, "Radiation Hardened Digital Direct Synthesizer with CORDIC for Spaceborne Applications", IEEE Access (ISSN: 2169-3536), Vol. 8, December 2020, pp. 83167-83176. DOI: 10.1109/ACCESS.2020.2991882. [IF(2020)= 3.367; Q2(2020)= 94/273].
  • F. García-Herrero, A. Sánchez-Macián, J.A. Maestro, "Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon’s Low-Complexity Chase", IEEE Transactions on Circuits and Systems II (ISSN: 1549-7747), Vol. 67, No 12, December 2020, pp. 3362-3366. DOI: 10.1109/TCSII.2020.2982496. [IF(2020)= 2.571; Q2(2020)= 81/319]
  • K. W. Gear, A. Sánchez-Macián, F. García-Herrero, J.A. Maestro, "Two Behavioural Error Detection Techniques for the Cascaded Integrator-Comb Interpolation Filter Implemented on FPGA", Circuits, Systems, and Signal Processing, Springer (ISSN: 0278-081X), Vol. 39, No 11, November 2020, pp. 5529–5542. DOI: 10.1007/s00034-020-01418-6. [IF(2020)= 2.225; Q3(2020)= 155/273]
  • A. Aranda, A. Sánchez, F. García-Herrero, Y. Barrios, R. Sarmiento, J.A. Maestro, "Reliability Analysis of the SHyLoC CCSDS123 IP core for Lossless Hyperspectral Image Compression using COTS FPGAs", Electronics, MDPI (ISSN: 2079-9292), Vol. 9, No 10, October 2020, pp. 1-15. DOI: 10.3390/electronics9101681. [IF(2020)= 2.397; Q3(2020)= 145/273]
  • García-Herrero, A. Sánchez-Macián, J.A. Maestro, M. Flanagan, "Extended symbol correction algorithm for group testing based non-binary error correction codes of minimum distance dq < 5", Microelectronics Reliability, Elsevier (ISSN: 0026-2714), Vol. 113, October 2020, pp. 1-5. DOI: 10.1016/j.microrel.2020.113724. [IF(2020)= 1.589; Q3(2020)= 196/273]
  • L. A. Aranda, A. Sánchez-Macián, J.A. Maestro, "A Methodology to Analyze the Fault Tolerance of Demosaicking Methods against Memory Single Event Functional Interrupts (SEFIs)", Electronics, MDPI (ISSN: 2079-9292), Vol. 9, No 10, October 2020, pp. 1-12. DOI: 10.3390/electronics9101619. [IF(2020)= 2.397; Q3(2020)= 145/273]
  • L. A. Aranda, P. Reviriego, J.A. Maestro, "Toward a Fault Tolerant Star Tracker for Small Satellite Applications", IEEE Transactions on Aerospace and Electronic Systems (ISSN: 0018-9251), Vol. 56, No 5, October 2020, pp. 3421-3431. DOI: 10.1109/TAES.2020.2971289. [IF(2020)= 4.102; Q1(2020)= 59/273]
  • F. García-Herrero, A. Sánchez-Macián, M. San-Isidro, L.A. Aranda, J.A. Maestro, "Efficient Majority-Logic Reed-Solomon Decoders for Single Symbol Correction", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 20, No 2, June 2020, pp. 390-394. DOI: 10.1109/TDMR.2020.2980754. [IF(2020)= 1.761; Q3(2020)= 186/273]
  • L. A. Aranda, A. Sánchez-Macián, J.A. Maestro, "An Algorithmic-Based Fault Detection Technique for the 1-D Discrete Cosine Transform", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ISSN: 1063-8210), Vol. 28, No 5, May 2020, pp. 1336-1340. DOI: 10.1109/TVLSI.2020.2969094. [IF(2020)= 2.312; Q3(2020)= 27/53]
  • L. A. Aranda, N.-J. Wessman, L. Santos, A. Sánchez-Macián, J. Andersson, R. Weigand, J.A. Maestro, "Analysis of the Critical Bits of a RISC-V Processor Implemented in a SRAM-based FPGA for Space Applications", Electronics, MDPI (ISSN: 2079-9292), Vol. 9, No 1, January 2020, pp. 1-12. DOI: 10.3390/electronics9010175. [IF(2020)= 2.397; Q3(2020)= 145/273]
  • J. C. Fabero, H. Mecha, F. J. Franco, J. A. Clemente, G. Korkian, S. Rey, M. Baylac and R. Velazco. "Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode," in IEEE Transactions on Nuclear Science, vol. 67, no. 7, pp. 1461-1469, July 2020, doi: 10.1109/TNS.2020.2977874 (JCR: Q2).
  • F. J. Franco, J. A. Clemente, G. Korkian, J. C. Fabero, H. Mecha and R. Velazco, "Inherent Uncertainty in the Determination of Multiple Event Cross Sections in Radiation Tests," in IEEE Transactions on Nuclear Science, vol. 67, no. 7, pp. 1547-1554, July 2020, doi: 10.1109/TNS.2020.2977698 (JCR: Q2).
  • M. Rezaei, P. Martín-Holgado, Y, Morilla, F. J. Franco, J.C. Fabero, H. Mecha. "Evaluation of a COTS 65-nm SRAM Under 15 MeV Protons and 14 MeV Neutrons at Low VDD," in IEEE Transactions on Nuclear Science, vol. 67, no. 10, pp. 2188-2195, Oct. 2020, doi: 10.1109/TNS.2020.3023287 (JCR: Q2).
  • Reza Ramezani, Juan Antonio Clemente, Francisco J. Franco, “Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets,” Reliability Engineering & System Safety, Volume 202, 2020, 107036, ISSN 0951-8320, DOI:10.1016/j.ress.2020.107036 (JCR: Q1).
  • G. Korkian, J. C. Fabero, G. Hubert, H. Mecha, M. Rezaei, F. J. Franco, H. Puchner, and J. A. Clemente. "Experimental and Analytical Study of the Responses of Nanoscale Devices to Neutrons Impinging at Various Incident Angles," in IEEE Transactions on Nuclear Science, vol. 67, no. 11, pp. 2345-2352, Nov. 2020, doi: 10.1109/TNS.2020.3025104 (JCR: Q2).
  • G. Hubert, S. Aubry and J. A. Clemente, “Impact of Ground Level Enhancement (GLE) Solar Events on Soft Error Rate for avionics”, in IEEE Transactions on Aerospace and Electronic Systems, Vol. 56, no. 5, pp. 3674-3684, 2020. (JCR: Q1)
  • D. Báscones, C. González and D. Mozos “An FPGA Accelerator for Real-Time Lossy Compression of Hyperspectral Images” Remote Sensing, Vol. 12, no. 16: 2563, 2020. (JCR: Q2)
  • D. Báscones, C. González and D. Mozos “An extremely pipelined FPGA implementation of a lossy Hyperspectral image compression algorithm”, IEEE Transactions on Geoscience and Remote Sensing, Vol. 58, no. 10, pp. 7435-7447, 2020. (JCR: Q1)
  • J.M. Catala-Perez, J.O. Lacruz, F. Garcia-Herrero, J. Valls, D. Declercq, “Second Minimum Approximation for Min-Sum Decoders Suitable for High-Rate LDPC Codes", Circuits, Systems, and Signal Processing, Springer, Vol. 38, No 11, November 2019, pp. 5068-5080, https://doi.org/10.1007/s00034-019-01107-z. (JCR: Q3).
  • D. Fernández, C. González, D. Mozos and S. López, “FPGA Implementation of the principal component analysis algorithm for dimensionality reduction of hyperspectral images”, Journal on Real Time Image Process, Vol. 16, no. 4, pp. 1395-1406, 2019. (JCR: Q2)
  • J. Valls, V. Torres, M.J. Canet, F. Garcia-Herrero, “A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding," IEEE Transactions on Circuits and Systems I, Vol. 66, No 6, June 2019, pp. 2198-2207, doi: 10.1109/TCSI.2018.2882876. (JCR: Q1).
  • V. Torres, J. Valls, MJ. Canet, F. Garcia-Herrero, “Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code," Electronics, Vol. 8, MDPI, 2019, https://doi.org/10.3390/electronics8010010. (JCR: Q2).
  • G. Perrone, J. Valls, V. Torres, F. Garcia-Herrero, “Reed-Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems," Circuits, Systems, and Signal Processing, Vol. 38, No. 4, April 2019, pp. 1793-1810, 2019, https://doi.org/10.1007/s00034-018-0938-x. (JCR: Q3).
  • A. Das, A. Sánchez-Macián, F. García-Herrero, N.A. Touba, J.A. Maestro, "Enhanced Limited Magnitude Error Correcting Codes for Multilevel Cell Main Memories", IEEE Transactions on Nanotechnology (ISSN: 1536-125X), Vol. 18, December 2019, pp. 1023-1026. DOI: 10.1109/TNANO.2019.2945341. [IF(2019)= 2.196; Q2(2019)= 75/155]
  • A. Sánchez-Macián, L.A. Aranda, P. Reviriego, J.A. Maestro, "Reducing False Positives Due to Double Adjacent Errors in Instruction TLBs", Microelectronics Reliability, Elsevier (ISSN: 0026-2714), Vol. 102, November 2019, pp. 1-6. DOI: 10.1016/j.microrel.2019.113494. [IF(2019)= 1.535; Q3(2019)= 182/266]
  • L. A. Aranda, A. Sánchez-Macián, J.A. Maestro, "ACME: A Tool to Improve Configuration Memory Fault Injection in SRAM-Based FPGAs", IEEE Access (ISSN: 2169-3536), Vol. 7, September 2019, pp. 128153-128161. DOI: 10.1109/ACCESS.2019.2939858. [IF(2019)= 3.745; Q1(2019)= 61/266]
  • A. Ramos, R. González-Toral, P. Reviriego, J.A. Maestro, "An ALU Protection Methodology for Soft Processors on SRAM-Based FPGAs", IEEE Transactions on Computers (ISSN: 0018-9340), Vol. 68, No 9, September 2019, pp. 1404-1410. DOI: 10.1109/TC.2019.2907238. [IF(2019)= 2.711; Q2(2019)= 19/53]
  • A. Sánchez-Macián, F. García-Herrero, J.A. Maestro, "Reliability of 3D Memories Using Orthogonal Latin Square codes", Microelectronics Reliability, Elsevier (ISSN: 0026-2714), Vol. 95, April 2019, pp. 74-80. DOI: 10.1016/j.microrel.2019.03.001. [IF(2019)= 1.535; Q3(2019)= 182/266]
  • Sánchez-Macián, L.A. Aranda, P. Reviriego, V. Kiani, J.A. Maestro, "Enhancing Instruction TLB Resilience to Soft Errors", IEEE Transactions on Computers (ISSN: 0018-9340), Vol. 68, No 2, February 2019, pp. 214-224. DOI: 10.1109/TC.2018.2874467. [IF(2019)= 2.711; Q2(2019)= 19/53]
  • L. A. Aranda, P. Reviriego, R. González-Toral, J.A. Maestro, "Protection Scheme for Star Tracker Images", IEEE Transactions on Aerospace and Electronic Systems (ISSN: 0018-9251), Vol. 55, No 1, February 2019, pp. 486-492. DOI: 10.1109/TAES.2018.2849919. [IF(2019)= 3.672; Q1(2019)= 64/266]
  • F. J. Franco, J. A. Clemente, H. Mecha and R. Velazco, "Influence of Randomness During the Interpretation of Results From Single-Event Experiments on SRAMs," in IEEE Transactions on Device and Materials Reliability, vol. 19, no. 1, pp. 104-111, March 2019, doi: 10.1109/TDMR.2018.2886358 (JCR: Q3).
  • G. León Navarro, C. González, R. Mayo Gual, D. Mozos and E. Salvador Quintana Ortí, “Noise estimation for hyperspectral subspace identification on FPGAs”, Journal of supercomputing, Vol. 75, no. 3, pp. 1323-1335. 2019. (JCR: Q2).
  • D. Báscones, C. González and D. Mozos, “Hyperspectral Image Compression Using Vector Quantization, PCA and JPEG2000”, Remote Sensing, Vol. 10, no. 6:907, 2018. (JCR: Q1).
  • D. Báscones, C. González and D. Mozos, “FPGA Implementation of the CCSDS 1.2.3 Standard for Real-Time Hyperspectral Lossless Compression”, IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing, Vol. 11, no. 4, pp: 1158 - 1165, 2018. (JCR: Q2)
  • C. Gonzalez, S. Lopez, D. Mozos, R Sarmiento, “A novel FPGA-based architecture for the estimation of the virtual dimensionality in remotely sensed hyperspectral images”Journal of Real-Time Image Processing 15 (2), pp. 297-308, 2018 (JCR: Q2)
  • J. Olivito, F. Serrano, J. A. Clemente, H. Mecha and J. Resano, “Analysis of the Reconfiguration Latency and Energy Overheads for a Xilinx Virtex-5 FPGA”, IET Computers & Digital Techniques, Vol. 12, no. 4, pp. 150-157, 2018. (JCR:Q3)
  • R. Ramezani, Y. Sedaghat, M. Naghibzadeh and J. A. Clemente, “A Decomposition-based Reliability and Makespan Optimization Technique for Hardware Task Graphs”, Reliability Engineering & System Safety (RESS), Vol. 180, Issue C, pp. 13-24, 2018. (JCR:Q1)
  • V. Torres, J. Valls, M. J. Canet and F. García-Herrero, "Soft-decision LCC Decoder Architecture with n=4 for RS(255,239)," 2018 16th IEEE International New Circuits and Systems Conference (NEWCAS), 2018, pp. 305-308, doi: 10.1109/NEWCAS.2018.8585684.
  • G. Perrone, J. Valls, V. Torres and F. M. García-Herrero, "High-Throughput One-Channel RS(255,239) Decoder," 2018 21st Euromicro Conference on Digital System Design (DSD), 2018, pp. 110-114, doi: 10.1109/DSD.2018.00032.
  • Francisco J. Franco and José Miguel Miranda Pantoja.  2019.  “Reliability Analysis of Electronic and Electrical Components of the LST Camera,”  CTA Engineering documents: Quality Analysis and RAMS. pp.1-53.
  • A. Ullah, P. Reviriego, A. Sánchez-Macián, J.A. Maestro, "Multiple Cell Upset Injection in BRAMs for Xilinx FPGAs", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 18, No 4, December 2018, pp. 636-638. DOI: 10.1109/TDMR.2018.2878806. [IF(2018)= 1.583; Q3(2018)= 171/266]
  • A. Cóbreces, A. Regadío, J. Tabero, P. Reviriego, A. Sánchez-Macián, J.A. Maestro, "SEU and SEFI Error Detection and Correction on a DDR3 Memory System", Microelectronics Reliability, Elsevier (ISSN: 0026-2714), Vol. 91, December 2018, pp. 23-30. DOI: 10.1016/j.microrel.2018.08.002. [IF(2018)= 1.483; Q3(2018)= 179/266]
  • L. A. Aranda, P. Reviriego, J.A. Maestro, "Protecting Image Processing Pipelines Against Configuration Memory Errors in SRAM-based FPGAs", Electronics, MDPI (ISSN: 2079-9292), Vol. 7, No 11, November 2018, pp. 1-10. DOI: 10.3390/electronics7110322. [IF(2018)= 1.764; Q3(2018)= 154/266]
  • R. González-Toral, P. Reviriego, J.A. Maestro, Z. Gao, "A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-based FPGAs", IEEE Transactions on Computers (ISSN: 0018-9340), Vol. 65, No 7, July 2018, pp. 1039-1045. DOI: 10.1109/TC.2018.2792445. [IF(2018)= 3.131; Q1(2018)= 11/53]
  • R. González-Toral, P. Reviriego, J.A. Maestro, C. Argyrides, "A Fast Technique to Reduce Power Consumption on Linear Block Codes Used to Protect Registers", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 18, No 2, June 2018, pp. 189-196. DOI: 10.1109/TDMR.2018.2812899. [IF(2018)= 1.583; Q3(2018)= 171/266]
  • A. Ullah, P. Reviriego, J.A. Maestro, "An efficient methodology for on-chip SEU injection in flip-flops for Xilinx FPGAs", IEEE Transactions on Nuclear Science (ISSN: 0018-9499), Vol. 65, No 4, April 2018, pp. 989-996. DOI: 10.1109/TNS.2018.2812719. [IF(2018)= 1.428; Q2(2018)= 12/34]
  • J. Tabero, A. Regadío, C. Pérez, J. Pazos, P. Reviriego, A. Sánchez-Macián, J.A. Maestro, "Modular Fault Tolerant Processor Architecture on a SoC for Space", Microelectronics Reliability, Elsevier (ISSN: 0026-2714), Vol. 83, April 2018, pp. 84-90. DOI: 10.1016/j.microrel.2018.02.011. [IF(2018)= 1.483; Q3(2018)= 179/266]
  • R. González-Toral, S. Liu, P. Reviriego, J.A. Maestro, "Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection", IEEE Transactions on Circuits and Systems I (ISSN: 1549-8328), Vol. 65, No 4, April 2018, pp. 1293-1302. DOI: 10.1109/TCSI.2017.2743248. [IF(2018)= 3.934; Q1(2018)= 57/266]
  • J. Martínez, J.A. Maestro, P. Reviriego, "Evaluating the Impact of the Instruction Set on Microprocessor Reliability to Soft Errors", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 18, No 1, March 2018, pp. 70-79. DOI: 10.1109/TDMR.2018.2796178. [IF(2018)= 1.583; Q3(2018)= 171/266]
  • A. Ullah, P. Reviriego, S. Pontarelli, J.A. Maestro, "Majority Voting-based Reduced Precision Redundancy Adders", IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 18, No 1, March 2018, pp. 122-124. DOI: 10.1109/TDMR.2017.2781186. [IF(2018)= 1.583; Q3(2018)= 171/266]
  • L. A. Aranda, P. Reviriego, J.A. Maestro, "A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response (FIR) Filters Implemented in SRAM-based FPGAs through Fault Injection", IEEE Transactions on Circuits and Systems II (ISSN: 1549-7747), Vol. 65, No 3, March 2018, pp. 376-380. DOI: 10.1109/TCSII.2017.2717490. [IF(2018)= 3.250; Q2(2018)= 80/266]
  • Z. Gao, M. Zhou, P. Reviriego, J.A. Maestro, "Efficient Fault Tolerant Design for Parallel Matched Filters", IEEE Transactions on Circuits and Systems II (ISSN: 1549-7747), Vol. 65, No 3, March 2018, pp. 366-370. DOI: 10.1109/TCSII.2017.2713479. [IF(2018)= 3.250; Q2(2018)= 80/266]
  • S. Liu, P. Reviriego, J.A. Maestro, L. Xiao, "Fault Tolerant Encoders for Single Error Correction and Double Adjacent Error Correction Codes", Microelectronics Reliability, Elsevier (ISSN: 0026-2714), Vol. 81, February 2018, pp. 167-173. DOI: 10.1016/j.microrel.2017.12.017. [IF(2018)= 1.483; Q3(2018)= 179/266]
  • A. Ramos, A. Ullah, P. Reviriego, J.A. Maestro, "Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs", IEEE Transactions on Computers (ISSN: 0018-9340), Vol. 67, No 2, February 2018, pp. 299-304. DOI: 10.1109/TC.2017.2737996. [IF(2018)= 3.131; Q1(2018)= 11/53]
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